1. Field
The present invention generally relates to the field of offset calibration for amplifiers.
2. Background
Analog-to-digital converters (ADCs) convert an analog input signal into a corresponding digital output signal. ADCs are implemented in many electronic applications such as, for example, quadrature amplitude modulation applications, digital televisions, and imaging applications. Oftentimes, ADCs are embedded in integrated circuits with stringent area and power requirements. It is thus desirable to avoid the need to trim the ADCs to achieve a required accuracy, as the process of trimming the ADC typically involves additional integrated circuits that occupy area and consume power.
However, in many ADC implementations, the matching of active devices oftentimes plays a significant factor in the accuracy of the ADC. For instance, mismatch in active devices of an amplifier used in the ADC can produce a DC offset, which can play a significant factor in the accuracy of the ADC. To increase accuracy in the ADC, the circuit area of the active devices in the amplifier (e.g., transistors that receive inputs to the amplifier) may be significantly increased (e.g., by 4 times) to achieve higher ADC resolution. This, in turn, can lead to low speeds and/or high power consumption by the amplifier. A tradeoff therefore exists between accuracy of the ADC and circuit area, speed, and power consumption of the ADC.
Apparatuses, methods, and systems are needed for calibrating offsets in amplifiers to achieve a high-resolution ADC, while minimizing circuit area and power consumption of the ADC.